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esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 1/11 1a cmos linear regulator general description the emp8995 low-dropout (ldo) cmos linear regulators feature low dropout voltage (510mv@1a), low quiescent current (120a), and fast transient response. it guarantees delivery of 1a output current and supports preset 3.3v output voltages. the regulator is stable with small ceramic capacitive loads (2.2f typical). the emp8995 is available in miniature sot-223 packages. applications g smps post regulator g dsp, fpga and microprocessor power g wireless devices g pc peripherals g lcd tv / monitors g portable handheld devices features g 1a guaranteed output current g 53db psrr @1khz, vout=3.3v, vin=4.3v, iload=1a g 30v rms output voltage noise @10ma g 510mv typical dropout at 1a g 120a typical quiescent current g less than 1na (typical) @ shutdown mode g fast line and load transient response g stable with small ceramic output capacitors g over temperature and over current protection g 2% output voltage tolerance typical application vin vout 13 2.2uf vin 2.2uf vout emp8995 gnd 2
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 2/11 connection diagram order information sot-223 (top view) sot-223 1 3 2 vin gnd vout EMP8995-XXVE03NRR xx output voltage ve03 sot-223 package nrr rohs & halogen free package rating: -40 to 85c package in tape & reel order, mark & packing information package vout product id. marking packing sot-223 3.3v EMP8995-XXVE03NRR pin1 dot 8995 tracking code 1 3 2 vin gnd vout tape & reel 3kpcs pin functions name sot-223 function vin 1 supply voltage input. require a minimum input capacitor of close to 2.2f to ensure stability and sufficient decoupling from the ground pin. gnd 2 ground pin. vout 3 output voltage feedback.
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 3/11 absolute maximum ratings (notes 1, 2) vin, vout -0.3v to 6.0v power dissipation (note 3) storage temperature range -65c to150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec.) 260c esd rating hbm 2kv mm 200v operating ratings (note 1), (note 2) temperature range -40c to 85c supply voltage vout+1v to 5.5v thermal resistance ( ja ) (note 3) sot-223 115c/w electrical characteristics unless otherwise specified, all limits guaranteed for v in = v out +1v, c in = c out = 2.2f, ta = 25c. boldface limits apply for the operating temperature extremes: -40c and 85c. symbol parameter conditions min typ max units v in input voltage 4.0 5.5 v -2 +2 v otl output voltage tolerance 100a i out 1000ma v out (nom) +1v vin 5.5v -3 +3 % of v out (nom) i out maximum output current average dc current rating 1000 ma i limit output current limit 1000 1300 ma i out = 0ma 120 i q supply current i out = 1000ma 350 a i out = 50ma 22 i out = 300ma 130 i out = 600ma 270 v do dropout voltage i out = 1000ma 510 mv line regulation i out = 1ma, (v out + 1v) v in 5.5v -0.15 0.1 0.15 %/v v out load regulation 1ma i out 1000ma 0.001 %/ma e n output voltage noise i out = 10ma, 10hz f 100khz 130 v rms thermal shutdown temperature 165 t sd thermal shutdown hysteresis 30 note 1: absolute maximum ratings indicate limits beyond which damage may occur. electrical specifications do not apply when operating the device outside of its rated operating conditions. note 2: all voltages are with respect to the potential at the ground pin. note 3: maximum power dissipation for the device is ca lculated using the following equations: ja a t - j(max) t d p = where tj(max) is the maximum junction temperature, ta is the ambient temperature, and ja is the junction-to-ambient thermal resistance.
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 4/11 functional block diagram fast start-up circuit current limit thermal protection error amp. + - r1 r2 vin vout gnd 1.19v bandgap fig.1 functional block diagram of emp8995
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 5/11 typical performance characteristics unless otherwise specified, vin = v out (nom) + 1v, c in = c out = 2.2f, t a = 25c. line transient (vout=3.3v, iout=10ma) line transient (vout=3.3v, iout=100ma) line transient (vout=3.3v, iout=500ma) li ne transient (vout=3.3v, iout=1000ma) load transient (vout=3.3v, iout=5 0ma to 500ma) load transient (v out=3.3v, iout=50ma to 1000ma)
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 6/11 typical performance characteristics (cont.) unless otherwise specified, vin = v out (nom) + 1v, c in = c out = 2.2f, t a = 25c. current limit (vout=3.3v) psrr vs. frequency
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 7/11 application information general description referring to fig.1as shown in the functional block diag ram section, the emp8995 adopts the classical regulator topology in which negative feedback control is used to perform the desired voltage regulating function. the negative feedback is formed by using feedback resistors (r1, r2) to sample the output voltage for the non-inverting input of the error amplifier, whose inverting input is set to the bandgap reference voltage. by virtue of its high open-loop gain, the error amplifier operates to ensure that the sampled output feedback voltage at its non-inverting input is virtually equal to the preset bandgap reference voltage. the error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage to the p-channel mos pass transistor to control the amount of current reaching the output. if there are changes in the output voltage due to load changes, the feedback resistors register such changes to th e non-inverting input of the error amplifier. the error amplifier then adjusts its driving voltage to maintain virtual short between its two input nodes under all loading conditions. in a nutshell, the regulation of the output voltage is achieved as a direct result of the error amplifier keeping its input voltages equal. this negati ve feedback control topology is further augmented by the shutdown, the fault detection, and the temperature and current protection circuitry. output capacitor the emp8995 is specially designed for use with ceramic output capacitors of as low as 2.2f to take advantage of the savings in cost and space as well as the superior filtering of high frequency noise. capacito rs of higher value or other types may be used, but it is important to make sure its equiva lent series resistance (esr) be restricted to less than 0.5 . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capacitors su itable for use with the emp8995 are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. no-load stability the emp8995 is capable of stable operation during no-load conditions, a mandatory feature for some applications such as cmos ram keep-alive operations. input capacitor a minimum input capacitance of 2.2f is required for emp8995. the capacitor value may be increased without limit. improper workbench set-ups may have adverse effects on the normal operation of the regulator. a case in point is the instability that may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will establish a pseudo lcr networ k, and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action thanks to its high esr. however, cautions should be exercised to avoid regulator short-circ uit damage when tantalum capacitors are used, for they are prone to fail in short-ci rcuit operating conditions. power dissipation and thermal shutdown thermal overload results from excessive power dissipation that causes the ic junction temperature to increase beyond a safe operating level. the emp8995 relies on dedica ted thermal shutdown circuitry to limit its total power dissipation. an ic junction temperature tj exceeding 165c will trigger the thermal shutdown logic, turning off the p-channel mos pass transistor. the pass tr ansistor turns on again after the junction cools off by about 30c. when continuous thermal overload conditions persist, this thermal shutdown action then results in a pulsed waveform at the output of the regulator. the concept of thermal resistance ja (c/w) is often used to describe an ic junction?s relative readiness in allowing its thermal energy to dissipat e to its ambient air. an ic junction with a low thermal resistance is preferred because it is relatively effective in dissip ating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. the relationship between ja and tj is as follows: t j = ja (pd) + t a t a is the ambient temperature, and p d is the power generated by the ic and can be written as:
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 8/11 p d = i out (v in - v out ) as the above equations show, it is desirable to work with ics whose ja values are small such that t j does not increase strongly with p d . to avoid thermally overloading the emp8995, refrain from exceeding the absolute maximum junction temperature rating of 150c under continuous op erating conditions. overstressing the regulator with high loading currents and elevated input-to-output differential volt ages can increase the ic die temperature significantly.
esmt/emp preliminary emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 9/11 package outline drawing sot-223 symbpls min. nom. max. a 1.80 a1 0.02 0.10 a2 1.50 1.60 1.70 b 0.66 0.70 0.84 b1 2.90 3.00 3.10 c 0.23 0.30 0.35 d 6.30 6.50 6.70 e 6.70 7.00 7.30 e1 3.30 3.50 3.70 e 2.30 bsc e1 4.60 bsc l 0.75 0 10 unit: mm
esmt/emp emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 10/11 revision history revision date description 0.1 2009.12.23 original
esmt/emp emp8995 elite semiconductor memory technology inc./ elite micropower inc. publication date : dec. 2009 revision : 0.1 11/11 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without th e prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt as sumes no responsibility for any error in this document, and reserves th e right to change the products or specification in this document without notice. the information contained herein is presented only as a guide or examples for the application of ou r products. no responsibility is assumed by esmt for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intelle ctual property rights of esmt or others. any semiconductor devices may have inherently a certain rate of failure. to minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly aff ect human lives or cause physical injury or property damage. if prod ucts described here are to be used for such kinds of application, pu rchaser must do its own quality assurance testing appropriate to such applications.

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